As processes continue to move to 0.13 micron and below, the challenge of ensuring signal integrity on a chip increases. Crosstalk between signals is the most severe problem that impacts signal timing, ...

Among the many verification challenges confronting system-on-chip (SOC) designers these days, clock domain crossings (CDCs) rank near the top in difficulty. The latest SOCs may have dozens or even ...

FIFO and handshake synchronizers pose special difficulties; new tools are the answer Among the many verification challenges confronting system-on-chip (SOC) designers these days, clock domain ...