EDN

An Overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
EDN

Cadence decries incompatible Verilog versions

Santa Cruz, Calif. – The EDA industry is risking “disaster” with two separate and incompatible versions of Verilog unless the Accellera standards organization quickly hands over SystemVerilog 3.1 to ...
Design-Reuse

How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1

Using advanced HDLs like SystemVerilog, current hardware modeling styles can be enhanced both in terms of abstraction levels and overall efficiency. By Sachin Kakkar, Sanjay Gupta, Ayan Banerjee, and ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

One of the beautiful things about SystemVerilog is that its verification capabilities can be adopted incrementally. One needn't swallow the entire language at once to make use of a given set of ...
Electronic Design

HDL Design Suite Gains SystemVerilog Support

Today, up to 80% of new ASIC and FPGA designs reuse RTL code from previous designs, and many design teams are embracing SystemVerilog, which was built with design reuse in mind. To support the ongoing ...
Design-Reuse

System Verilog based Generic Verification Methodology for IPs/ASICs/SOCs: A Case Study

This document discusses Random constraint-based verification and explains how random verification can complement the directed verification for the generic designs. In our case this is demonstrated by ...