• Designed a generic Cache simulator module and modeled L1, L2 caches augmented with a Victim Cache. • Implemented using C++ and evaluated with SPEC address traces for gcc, perl, vortex, compress and ...

The dynamic interplay between processor speed and memory access times has rendered cache performance a critical determinant of computing efficiency. As modern systems increasingly rely on hierarchical ...

These are exciting times for the memory hierarchy in systems. New kinds of DRAM and non-volatile memories are becoming available to system architects to enhance the performance and responsiveness of ...

Gaps in the memory hierarchy have created openings for new types of memory, and there is no shortage of possibilities. It’s no secret that today’s memory chips and storage devices are struggling to ...

A technical paper titled “RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory” was published by researchers at ETH Zürich, KMUTNB, ...

The gap between the performance of processors, broadly defined, and the performance of DRAM main memory, also broadly defined, has been an issue for at least three decades when the gap really started ...

Developed a flexible cache simulator which implemented L1 cache, its Victim cache and L2 cache. Analyzed the performance of various memory hierarchy configurations with varying parameters and ...