EDN

Managing variations in IC physical design

At nanometer technologies, variability is rapidly becoming one of the leading causes for chip failures and delayed schedules. However, there is significant confusion about the term “variability” in ...
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...
Design-Reuse

Using in-design physical verification to reduce tapeout schedules

. Tadahiko Yamamoto is Chief Specialist, Design Methodology Development Group, at Toshiba Corp. . Norikazu Ooishi is Specialist, Design Methodology Group, at Toshiba Corp. Physical designers moving to ...
Design-Reuse

Top-down SoC Design Methodology

Deep sub-micron effects complicate design closure for very large designs. Top-down hierarchical design methodology combined with physical prototyping increases design productivity and restores ...
EDN

Physical Design Flow Taps Partition Layout

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.
Semiconductor Engineering

Hyperconvergence Of Design For Test And Physical Design

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...
Semiconductor Engineering

Optimizing For Energy In Physical Design

Energy is a precious resource, which should not be wasted. Energy drives economies and sustains societies. Predictions show that the energy of electronics may soon consume 20% to 33% of the global ...